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Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.

It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.

Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.

Machine learning is gradually moving into implementation and verification tools for EDA.

IoT device makers should play more with their software and make use of techniques used in website design to increase overall usability, Amazon’s head of IoT analytics has claimed.

Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.

Deal to buy functional safety specialist builds out the automotive and Industry 4.0 offerings for Mentor and its parent Siemens.

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.

At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.