As the Design Automation Conference (DAC) proceeded in San Francisco last week (25-28 June, 2018), Accellera published the first release of the Portable Test and Stimulus Standard (PSS), with support announced by Breker Verification Systems, Cadence Design Systems and Mentor, a Siemens business.
Accellera chair Lu Dai said he expects the standard to “have a profound impact on the industry as a whole” by providing a way of building test scenarios that can be applied across multiple situations and platforms. Dai told TDF the working group is one of the most active at Accellera and is already working on updates based on feedback from the user community. “The team is not slowing down at all,” he noted.
The standard is available to download for free at Accellera’s website. It defines a specification to create a single representation of stimulus and test scenarios, usable by a variety of users across many levels of integration under different configurations. The execution platforms can span simulation, emulation, FPGA prototyping, and post-silicon, among others. With this standard, users can specify a set of behaviors once and expect to observe consistent behavior across different environments. PSS supports two different types of input for creating test scenarios. One is a domain-specific language created specifically for the purpose; the other is a set of class declarations for use with C++.
Mentor, which started work on graph-based portable-stimulus concepts in 2004, said it will fully support the new Accellera Portable Test and Stimulus Standard 1.0 in the upcoming release of its Questa inFact tool.
“When Mentor donated the Questa inFact tool’s language and initiated the original Accellera Portable Test and Stimulus Working Group in 2014, we did so to drive portable stimulus toward mainstream use and help more design teams realize the step-function gains in verification productivity afforded by our Questa inFact tool,” said Mark Olen, product marketing group manager for Mentor’s IC verification solutions division.
Cadence said its Perspec System Verifier supports the version 1.0 standard, providing what the company calls an “abstract model-based approach” for defining SoC use-cases from the PSS model. The tool uses Unified Modeling Language (UML) activity diagrams to visualize the generated tests.
Breker has also claimed full compliance with the version 1.0 standard for its Trek5 portfolio of tools.
EDA companies such as Mentor have seen opportunities to use the test scenarios, which are built using declarative-programming techniques based on actions, schedules and constraints, to support greater degrees of automation. Mentor said it has applied classification machine learning to the graph-based technology in Questa InFact to enable the better targeting of scenarios to achieve coverage goals at the IP block level and increased usefulness of bare metal testing at the IC level. The tool learns from each subsequent scenario during simulation or emulation.
Mentor has also applied data mining technology to extend the application of portable stimulus beyond verification. The Questa inFact tool can collect and correlate transaction-level activity to characterize IC design performance parameters including fabric routing efficiency and bandwidth, system-level latency, cache coherency, arbitration efficiency, out-of-order execution, and even opcode performance. It can also analyze regression test environments to help eliminate redundant simulation and emulation cycles.