IP

Agile Analog has moved into the supply of cores for detecting hardware-hacking attempts as well as more conventional data-conversion modules.

Emulation capacity and its scalability is a major issue for large SoC designs, said panelists at DVCon Europe.

In a panel at this week’s DVCon Europe, experts described a number of issues facing teams looking to incorporate machine learning in logic verification flows and why some of those efforts will not pay off while others succeed.

Arm’s SystemReady program has revealed a number of the subtleties involved when trying to maintain software compatibility with operating systems without moving to the straightjacket of platforms like those used for the x86-based PC.

Arm has used machine-learning tools supplied by the Solido group at Siemens Digital Industries Software to speed up IP validation runtime a thousand-fold compared to conventional statistical methods.

Siemens EDA has become the first of the major EDA vendors to join the DARPA Toolbox Initiative.

Cadence has organized its machine-learning platforms into three families intended to cover a wide range of on-device AI applications.

Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.

Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.

The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.