Accellera approves IP security-documentation standard
Accellera has approved version 1.0 of the SA-EDI standard, intended to provide a consistent way of describing security concerns for IP cores.
IP
Xilinx retools Versal for high-end edge AI
Xilinx has reworked its Versal FPGA for edge-AI applications.
Three libraries tune speed and density on TSMC’s 3nm process
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Arm rolls clickthrough license scheme into Flexible Access
Arm is reworking the DesignStart scheme it introduced several years, moving it under the umbrella of the broader Flexible Access program.
Denser DRAM looks to flash for inspiration
Unisantis aims to use its vertical transistor design in a novel form of DRAM that could improve density four-fold.
Edge AI focuses on power efficiency at Linley Spring
The Linley Spring Conference saw several vendors present architectures that they claim can deliver more performance to edge systems than what are now traditional approaches.
Portable stimulus moves to version 2.0
The Accellera board has approved version 2.0 of the Portable Test and Stimulus Standard.
Accellera publishes security standard draft
Accellera has published the version 1.0 draft of the proposed Security Annotation for Electronic Design Integration standard.
Arm looks to explore new realms for security with v9
Arm aims to introduce a novel security model in its upcoming v9 architecture along with further extensions for AI.