EDA

DAC 2013's technical program has four sessions on innovation for verification. Some of the hot topics being covered include 3DIC and analog.

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.

Whether your going to DAC 2013 or not, the EDA analyst's round-up is an invaluable guide to design trends and the tool vendors most actively addressing them.

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.

Real Intent and DeFacTo Technologies combine clock-domain crossing and design for test tools in RTL sign-off flow.

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.

The fifth generation of Forte Design System's Cynthesizer tool is a slice of system-level evangelism.

But you can still get in for free by registering for the 'I Love DAC' scheme by this Friday (May 17th).