DAC 2013 Preview VIII: Low-power design

By Chris Edwards |  No Comments  |  Posted: May 22, 2013
Topics/Categories: Blog - EDA  |  Tags: , ,

As Austin is the city of processors, including the PowerPC that sits inside a good many server-class computers, the conference has a strong focus on lowering power consumption in the data center. The conference kicks off at the other end of things with Freescale Semiconductor’s Gregg Lowe talking about the SoC landscape for the Internet of Things – devices that are crying out for low-energy techniques.

Tuesday’s keynote by Nam Sung Woo of Samsung will look at the other key market for low-power design: smart mobile devices.

Even before the conference proper gets going, a Sunday workshop looks at the 2013 revision of the IEEE P1801 standard – in effect the grand merger of CPF and UPF. An additional meeting on Tuesday brings together representatives from the IEEE committee and the Silicon Integration Initiative (Si2), which administers CPF.

Here are some of the key sessions on low power that we’ve spotted in the DAC schedule.

Sunday June 2

Low-Power Design with the IEEE 1801-2013 Standard
1:00 PM – 5:00PM, Workshop, Room 18C
The workshop will cover an introduction to the low power design intent concepts and methodologies fundamental to IEEE 1801, as well as detailed discussion of the main changes from the previous version (IEEE 1801-2009). The workshop will concentrate on the standard, its underlying semantics and intended methodologies, in the eyes of the expert 1801 working group members, illustrated by real world examples.

Monday June 3

Avoiding Core Meltdown! – Adaptive Techniques for Power and Thermal Management of Multi-Core Processors
11:00 AM – 1:00PM, Tutorial, Room 18C

The objective of this embedded tutorial is to bring DAC attendees who are interested in low-power design for high-end, multi-core processors to the forefront of the latest academic research and industrial practice in the area of closed-loop control of power and temperature in multi-core processors. Attendees don’t have to have any background in control theory.

Monday June 3

Cloud Server War – Embedded Processor Battle Ground: Austin
1:30 PM – 3:00PM, Designer Track Panel, Hall 5

Cloud computing is a fast growing market for data centers. But, it imposes new challenges to Server Chip architectures (such as low power, virtualization, security, embedded software compatibility to name a few). Austin is an embedded processor battleground. Let’s hear how companies (using disruptive technologies) are going to tackle these new challenges and how cloud computing could change your lives. The panel will also have end users with the unique perspective of the role of embedded systems in the success for cloud storage, search, and computing.

Tuesday June 4

I Blew My Power Budget: Whom Should I Throw Under the Bus?
1:30 PM – 2:30PM, Technical Panel, Room 16AB

During the last phases of the design, or even after first silicon, I discover that the power budget is blown. What can I do at this point? Whom do I blame? What should I do to ensure this does not happen again? The panelists will tell their horror tales. Let’s see who gets thrown under the bus…

Tuesday June 4

Emerging Application-Oriented, Low-Power Techniques
4:00 PM – 6:00PM, Paper Session, Room 15

This session covers a lot of ground, from low-power memory based on the Racetrack technology to system-level power models. However, there is a strong emphasis on system-level, adaptive energy-management techniques. One paper from Syracuse University, for example, looks at scheduling when data should be stored to memory in energy-harvesting systems. And researchers from the Georgia Institute of Technology will talk about a use-aware MIMO RF receiver.

Wednesday June 5

System Power Estimation and Performance Verification
9:00 AM – 10:30 AM, Paper Session, Room 18C

The session describes a number of techniques for early validation of power and modeling power consumption at the system level as well as a paper on closed-loop control for multicore processors that follows on from the theme of the Monday tutorial session, and which is a best-paper candidate for the 2013 conference.

Thursday June 6

Power and Performance
3:30 PM – 5:30 PM, Designer Track, Room 18C

The presentations in this session focus on design experiences with techniques for validating and optimizing power/performance as part of the front-end RTL design process. Cisco Systems will talk about hierarchical verification of low-power designs and Intel is focusing on power-aware emulation for CPU design. Broadcom will look at the issues of verifying systems that use partial state retention with power gating.

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