Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
The encryption chain for today's highly collaborative designs needs to be managed with care.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
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