Using on-demand rule checks during place-and-route boosts efficiency and design quality.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
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