An easier way to make reliability rules and checks more consistent
Learn how XML-based constraints can standardize rule development and use with coding examples for the Calibre PERC reliability platform.
DFM
AI firsts (and more) at America’s SEMICON
SEMICON West showed a distinct thematic shift away from preserving Moore's Law to assessing the architectural implications of AI, as EDA was brought into the event.
Optimize your database with duplicate data deletion
Whether you use OASIS or GDSII, unwanted duplicate cells can make their way into the final SoC database. Learn how to remove them.
Preparing for success at the next node with Calibre
How Mentor develops and works with partners to prepare each version of its Calibre DFM platform to be ready for the introduction of each new process node.
How critical area analysis improves yield
CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
Use evolving DRC to automate high-voltage and multi-power domain verification
Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Validating on-chip variation: Is your library’s LVF data correct?
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
Fast, accurate layout merging for SoC flows
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
Enhanced model-based hinting may be the edge you need below 20nm
A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
EUV’s arrival demands a new resolution enhancement flow
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
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