April 28, 2022
What are the options and how do you balance overarching CAD requirements and personal preferences?
March 3, 2022
Because of the high analog content in memory designs, designers must understand how various effects impact reliability and performance.
October 21, 2021
Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
August 25, 2020
How Calibre is evolving to address the challenges of LVS verification in early-stage design.
June 11, 2019
How to remove or extract portions of a layout for easier, more focused and faster project delivery.
May 31, 2018
The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
December 22, 2017
In-design DRC is a technique that frees up engineers from many of the challenges of delivering AMS design under ever more complex design rules.
September 14, 2017
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
October 3, 2016
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
January 13, 2014
Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.