How to optimize productivity and accuracy in IC design and verification flows
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
DRC waivers
Not using reliability check waivers? You’re wasting valuable time
Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
Managing waivers in reliability verification
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
How to use pattern matching to improve automatic waiver management
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
Improving SoC productivity through automatic design rule waiver processing for legacy IP
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
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