A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
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