How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
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