Design space exploration finds hotspots during early process development
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
DFM
Three ways to lift productivity during physical verification
How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Assessing the true cost of node transitions
John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
Catch multi-patterning errors clearly at advanced nodes
How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Yield is money – and other truths of diagnosis-driven yield analysis
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
Silicon photonics moves out of the shadows
An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
Your next node: find lithography issues early with DTCO
Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
The Wally Rhines interview – Part One: Mentor as a Siemens business
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
How Applied Materials and fab partners are harnessing machine learning
The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
How place and route is adapting to challenges below 10nm
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
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