How AI improves DFT, test and yield
Take a high level view of the AI strategies used within the Tessent family to improve across-the-board performance.
Tessent
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
Slash test time by combining hierarchical DFT and channel sharing
A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Yield is money – and other truths of diagnosis-driven yield analysis
Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
Accelerate silicon bring-up in a bench-top environment
How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
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