Tessent

March 22, 2021

Silicon lifecycle solutions help you listen to your chip

SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
July 9, 2018
Channel sharing and hierarchical DFT - Featured Image

Slash test time by combining hierarchical DFT and channel sharing

A hierarchical methodology removes DFT from the critical path for large designs. The methodology is compatible with other techniques such as channel sharing, which can further reduce ATPG turn-around time and test cost.
Article  |  Topics: EDA - DFT  |  Tags: , , , ,   |  Organizations:
September 21, 2017

Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
January 10, 2017
Silicon bring-up Tessent

Accelerate silicon bring-up in a bench-top environment

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
Article  |  Topics: EDA - DFT, - EDA Topics  |  Tags: , ,   |  Organizations: ,

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