Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
DVCon China general chair Andy Liu discusses Accellera’s new addition to its design and verification conference series (简体中文).
AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?
The next boost to verification productivity will come from the integration of multiple strategies and tools.
The chipmaker used Calypto’s PowerPro to carry out power analysis of its latest core design at the RTL rather than at post-gate synthesis.
OpenCL aims to open up the performance of graphics processors to other applications. It is also one more way in which compilation is being moved to runtime to make it easier to move code dynamically across heterogeneous platforms.
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