Tech Design Forums
Technique
physical design
physical design
All
(2)
Articles
(2)
January 27, 2022
Aim for power first for best place-and-route results
The strategy of designing for best power rather than for best timing in place-and-route delivers better results all around.
Expert Insight | Topics:
EDA - IC Implementation
| Tags:
low-power design
,
physical design
,
place and route
,
PPA
October 3, 2016
How place and route is adapting to challenges below 10nm
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
Article | Topics:
EDA - DFM
,
- EDA Topics
,
EDA - IC Implementation
| Tags:
cell pin access
,
double patterning
,
finFET
,
layout
,
minimum jog
,
multi-patterning
,
oxide diffusion
,
physical design
,
pin to track
,
place and route
,
submetal shape
| Organizations:
Mentor Graphics
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
PLATINUM SPONSORS
View All Sponsors
twitter
facebook
RSS
Tech Design Forum
Log In
Register
Sponsors
Briefing
EDA
EDA TOPICS
DFM
DFT
ESL
IC Implementation
Verification
MORE EDA
Expert Insights
Guides
EDA Home Page
IP
IP TOPICS
Assembly & Integration
Design Management
Selection
MORE IP
Expert Insights
Guides
IP Home Page
PCB
PCB TOPICS
Design Integrity
Layout & Routing
System Codesign
MORE PCB
Expert Insights
Guides
PCB Home Page
Embedded
EMBEDDED TOPICS
Architecture & Design
Integration & Debug
Platforms
User Experience
MORE EMBEDDED
Expert Insights
Guides
Embedded Home Page
Search