Master parasitic extraction for leading-edge designs
A comprehensive guide to parasitics, how to perform parasitic extraction and the latest technologies available for this critical task.
DFM
Simplify and accelerate PV debug using default results data views
Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
Improved power management and faster time to market?
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
Six reasons why you need better cross-platform validation of OASIS layout database generation
You must understand six comparison concerns and their effect on database equivalency. Adopt a solution with an in-depth object-based approach.
Give the people what they want: toward making 3D IC mainstream
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
Building confidence and flexibility in 3D-IC system level design
3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
A quick and easy way to calculate P2P resistance and current density
Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
Layout customization improves productivity in design and verification flows
What are the options and how do you balance overarching CAD requirements and personal preferences?
Siemens’ Sawicki puts priority on scaling in processes, productivity and systems
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
How to optimize productivity and accuracy in IC design and verification flows
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.