Using on-demand rule checks during place-and-route boosts efficiency and design quality.
A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
In a continuous-build design flow, at which level should your error markers be addressed?
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
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