place and route

September 21, 2020
filler cells featim sep20

P&R filler cell insertion slowing you down? Replace it

A physical verification-ready flow can speed project delivery by making your use of filler cells more efficient.
Article  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
June 9, 2020
place and route in design automated hotspot fixing

How to achieve fast, automated, sign-off verification of DFM hotspot fixes in P&R

A collaboration between GlobalFoundries and Mentor has resulted in an innovative in-design fixing strategy across markets such as IoT, mobile, RF, graphics and networking.
March 17, 2020
FeatIm P&R MaxLinear Mentor

How MaxLinear got faster signoff DRC while optimizing reliability and manufacturability

The RF and AMS specialist turned to design software that allowed it to run design checks during place and route.
January 25, 2019

A better way to manage error reporting at the chip and block levels

In a continuous-build design flow, at which level should your error markers be addressed?
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations:
March 9, 2018
Saunder Peng is a Senior Application Engineer with Mentor, a Siemens Business. He received his B.S degree in Electrical Engineering from the University of California at Los Angeles, and his M.S. in Electrical Engineering from Columbia University, New York.

A better way to merge design files for physical verification

Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
October 18, 2014
Soft-blocked floorplan

Placement optimizations push power and clock on Cortex-M7 project

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.
January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Multiple patterning is causing issues with access to standard-cell pins in nanometer processes

Cell pin access

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
September 24, 2013

Accelerating process migration in advanced ASIC design at Bull

How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Article  |  Topics: IP - Design Management, EDA - IC Implementation  |  Tags: , , ,   |  Organizations: ,

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