Synopsys adds vector DSP operations to ARC EM processor IP

By Chris Edwards |  No Comments  |  Posted: May 29, 2014
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations:

Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family of deeply embedded cores based on the ARC version 2 architecture. The company has deployed it in two EM-series cores designed to provide ‘always on’ signal processing for handheld and internet of things (IoT) applications.

The ARCv2DSP instruction set architecture adds more than 100 instructions, including complex-arithmetic multiply and multiply-accumulate (MAC) instructions. An implementation designed to run Sensory’s TrulyHandsFree voice-activation algorithms, which needs a clock speed of just 230kHz to operate, consumes 4µW on a 28nm HPM process.

“There has been a rapid proliferation of feature-rich mobile and IoT electronics needing instantaneous responses to audible commands or movements,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys.

The DSP instruction set provides support for saturating arithmetic, with rounding and non-rounding modes for integer and fractional integer datatypes, such as the Q15 and Q31 datatypes that are commonly used in the intrinsics libraries of other common integer DSPs. The DSP uses a 32x32bit multiply unit to support either single multiplies and MACs or dual vector or complex-maths operations.

One of the cores is an extension to the EM7, with a lower-end version, the EM5 that is roughy analogous to the original EM4. The DSP versions of the cores can have larger closely coupled memories than the originals – upt to 2Mbyte. They retain the EM’s three-state pipeline.

Synthesized for power and area to a 40nm LP process, the EM5D consumes around 7µW/MHz and around 0.4mm2 of die space. The baseline EM4 takes up 0.014mm2 on a 40nm LP process, consuming 4.4µW/MHz. If tuned for performance, the EM5D and EM7D can hit a frequency of 530MHz, Synopsys said.

Like their general-purpose counterparts, a floating-point unit can be added to the processors and they retain support for user-defined instructions. The MetaWare compiler and toolset includes a software library of fixed-point maths functions and an instruction-accurate simulator.

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