IP takes center stage in push towards systems engineering

By Chris Edwards |  1 Comment  |  Posted: May 29, 2014
Topics/Categories: Blog - EDA, IP  |  Tags: , ,  | Organizations: , , , , , ,

During his Monday morning keynote at DAC 51 in San Francisco, Imagination Technologies CEO Hossein Yassaie will claim IP is coming to the rescue of SoC designers – by providing an increasing proportion of the content of each project. The rest of the cavalry will turn up in the exhibit hall: 11 out of the 17 first-time exhibitors at DAC are in IP, design services or both.

Overall, some 30 per cent of the exhibitors represented at the Moscone from 2 June to 4 June now work in the IP and design services space. Two of the ‘villages’ on the exhibit floor are centred around IP companies: ARM and IP distributor IP Extreme. When you consider that the number of reused cores on a leading-edge SoC has now surpassed 100, according to IBS, it is easy to see why this has become a key business to be in.

The big get bigger

However, Gartner warns in a research note published on 28 May 2014 that the push to buy IP at the platform level may push the smaller players who have sprung up out of the market. ARM, Synopsys, Imagination Technologies, and Cadence now dominate high-growth IP segments such as microprocessors, graphics, memory blocks, wired interfaces and subsystems, Gartner said, with a 78 per cent share of total segment revenue.

Gartner said the Herfindahl-Hirschman Index (HHI) for the semiconductor design IP market moved up by 376 points to 2185 in 2013 from 1809 in 2012. This indicates increasing market concentration and worsening conditions for small and midsize IP suppliers. But the interest in the Internet of Things (IoT) and its requirement for analog cores and interfaces as well as specialized low-power processors may stem the tide flowing towards the big four.

A good proportion of the IP exhibitors are specialists in mixed-signal IP, including first-time exhibitor S3 Group from Ireland, which has developed technology for low-power successive-approximation analog-to-digital converters, among other things. The growth reflects a trend observed by market analyst Semico Research in March this year. The company reported that mixed-signal ASIC and SoC designs are now growing strongly, in a market that has turned around in recent years following a long-term decline in design starts. The total number of ASIC design starts will increase just over 7 per cent, Semico reported.

A decade-long process

If we rewind ten years to 2004, it’s worth having a second look at what Raul Camposano, then CTO of Synopsys (before stepping into the mixed-signal simulation business), said. Asked about the prospects for system-level design and the prospects for high-level synthesis, he countered: “You can use synthesis or you can use IP. IP is the only model that scales.”

Over the next ten years, the question is how an IP-centric design strategy will cope with the need to reduce power and deal with system-level issues. How do you change the architecture of a system when so many parts of it are fixed? Can you find ways to model a system of connected cores from the bottom up, without it taking eons to finish, and then use that understanding to tune the cores and the interconnect scheme that links them?

DAC 51 speakers such as Intel’s Shekhar Borkar – he gives a Sky Talk on Tuesday, 3 June – have identified the need for a more systemic approach to SoC design, for example moving intelligence into memory and restructuring the way that software works. It seems unlikely that companies will drop the IP-based design strategy, but can the IP industry become flexible enough fast enough to deal with the transition from SoC design as block assembly to SoC design as systems engineering?

Models and algorithms combine

There are some glimmers. One of the first-time exhibitors I didn’t tag as ‘IP’ was Imperas, which offers fast system-level models of processor cores and has branched out into tools for software and system-level analysis. They are not so much tools as toolkits, designed to let architects develop ways to track a system to give them insights into system-level behavior, such as multicore cache usage and the way data moves between them. Imperas will be in the ARM village.

Take also NetSpeed Systems, which is applying insights developed in architecting large computing and telecoms networks to the problem of designing effective on-chip networks. By borrowing from the macro scale, it doesn’t need to reinvent solutions to solved problems at the nano scale.

IP makes it possible to assemble large amounts of functionality onto a single IC, and we seem to know how to do that. Finding a way to develop true systems on chip as effectively will take a shift in designer mindset, design tools and IP block architectures to reflect the fact that advanced chip design is now really advanced systems design.

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