ISSCC 2013: IBM adds digital logic synthesis methodology for System z
The paper on the 32nm upgrade to Big Blue's family of server chips also detailed how the company is tackling BTI.
IBM
Cadence updates Virtuoso for the 20nm generation
Cadence Design Systems has built into its latest Virtuoso update features designed to tackle the problems of working with the 20nm generation of processes with finer control over layout-dependent effects, double patterning and new types of local interconnect.
3D-IC integration prospects improving, say IEDM researchers
3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM
FD-SOI vs finFETs mulled during IEDM
Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs
Semiconductor roadmap gets fuzzier at IEDM
Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs
FinFETs face planar fightback at IEDM
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Doping gives finFETs threshold control
You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.