Real Intent’s Pranav Ashar on converging design and verification
Verify early and simulate as little as possible - the idea is familiar but how do you get there?
EDA
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Mentor’s Wally Rhines on tools as a cultural issue
Whether you're going to DAC this week or not, it's worth remembering one of the other key factors that will inform your judgments on new tools.
Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Synopsys adds vector DSP operations to ARC EM processor IP
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.
IP takes center stage in push towards systems engineering
At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
Real Intent updates lint tool, adds Matlab and Simulink support
More lint rules, better SystemVerilog support, links to MATLAB and Simulink
Mentor seeks component data in PCB design tie-up with Digi-Key
Digi-Key is to sell software developed by Mentor Graphics intended to widen access to PCB design and ease access to vital parts data.
Pulsic opts for “layout early, layout often” strategy
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Verification perspectives 2: formal for the masses and graph-based techniques
The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.