Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Archives
Ceva extends control-oriented DSP
Ceva has followed its IoT-oriented Ceva-X series of processor cores with a more powerful family that is designed to handle control and signal-processing algorithms using the same pipeline.
Closing code coverage with a hardware-aware HLS-to-RTL flow
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Synopsys announces DDR5 and LPDDR5 interface IP
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
IEDM shows progress on embedded eMRAM
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Microchip opts for RISC-V cores in SoC FPGA
Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
Leti takes the heat off monolithic 3D
CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
Achronix builds machine learning IP into eFPGA
Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.
Design Compiler updated for 5nm and beyond
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.