formal verification

May 21, 2015

Agnisys automates register checks

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
May 21, 2015

Real Intent tackles CDC at the physical level

Meridian Physical CDC targets post-synthesis gate-level clock domain crossing issues, including unintended glitches and functional failures.
May 11, 2015

Formal verification conference offers ARM, Broadcom, Imagination insights, online access

Conference addresses formal verification techniques at levels to suit beginners through to experts
September 29, 2014

Verification platform offers unified compile, debug environments

Synopsys is integrating its verification tools to make it easier to move between verification approaches for software centric SoCs
Article  |  Topics: Blog Topics, Verification  |  Tags: , , , , , , ,   |  Organizations:
June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
May 21, 2014

Verification perspectives 2: formal for the masses and graph-based techniques

The second part of our interview with Mark Olen and Jim Kenney, looks at how formal and graph-based techniques move the market beyond simulation.
April 22, 2014

Cadence to expand formal portfolio with Jasper buy

Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations: ,
March 4, 2014

Synopsys targets 5X performance gain with integrated verification suite

New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
January 14, 2014

Cadence updates Incisive with formal, CRV, wreal additions

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
November 20, 2013

Complexity to force shift to four-stage verification

The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors