July 30, 2020
Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
July 27, 2020
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
July 16, 2020
Mentor, a Siemens Business, will offer a broad range of technical and market insights at the event – as well as a free virtual coffee for those who visit its virtual booth at the show.
March 30, 2020
Updates to existing designs are often error-prone, though safety tolerances are necessarily tightening. This four-step strategy can help.
January 29, 2020
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
October 29, 2019
Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
May 28, 2019
OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference's Designer Track.
May 24, 2019
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
May 8, 2019
Cadence and OneSpin are applying various forms of machine learning to their tools to automate formal verification.
February 26, 2019
Tools that checks pre-synthesis C++ and SystemC code have historically had no understanding of hardware intent. The Catapult Design Checker fills that gap.