formal verification

November 5, 2013

Formal app looks for sneak paths in secure chips

Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
October 30, 2013

The prospects for GALS: Real Intent’s view

Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
October 17, 2013

Uptake of formal techniques in verification to be outlined in keynote

Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
Article  |  Topics: Conferences  |  Tags:   |  Organizations:
June 17, 2013

Synopsys doubles speed of formal ECO checking

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Article  |  Topics: Design to Silicon, RTL, Verification  |  Tags: ,   |  Organizations: ,
May 14, 2013

Jasper adds low-power App to formal family

Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
October 17, 2012

Mentor extends Questa with formal coverage checks

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
June 6, 2012

DAC 2012: A look inside Accellera’s UCIS

Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.

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