April 22, 2014
Cadence Design Systems has reached an agreement with Jasper Design Automation to buy the formal-verification specialist for $170m in cash.
March 4, 2014
New tool technologies, Verdi integration and greater flow concurrency also contribute to a claimed 3X increase in productivity for Verification Compiler.
January 14, 2014
Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
November 20, 2013
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
November 5, 2013
Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
October 30, 2013
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
October 17, 2013
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
May 14, 2013
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
October 17, 2012
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.