Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Jasper Design Automation's modular concept moves into a hot area in SoC design to verify specs are still met after power management circuitry is inserted.
New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.
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