Remembering Colin Holland
The respected electronics journalist and our friend passed away this Thursday at 59.
Author Archives: TDF Staff
FinFET tipsheet for IEDM
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
IJTAG: delivering an industry platform for IP test and integration
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
3DIC – the advantages and the challenges of vertical integration
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Embedded systems are evolving, but where are the tools?
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
The physical design challenges of 20nm processes
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Virtual prototyping moves further into the mainstream
Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.
Getting ready for 20nm
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
Verification challenges require surgical precision
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Why cell-aware testing is important
Characterizing standard-cell defect mechanisms helps improve IC testing