Author Archives: TDF Staff

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

Characterizing standard-cell defect mechanisms helps improve IC testing

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.

This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.

Cutting the cabling to simplify the emulation process.

Companies need to collaborate with partners, vendors, and the rest of the supply chain if they are to achieve critical mass, Aart de Geus tells Synopsys user meeting.

Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey

This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.