Author Archives: TDF Staff

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.

This newsletter highlights recently-added content on the site that addresses the connected areas of verification, prototyping and emulation. We’ve also added more overview EDA Guides on major design flow challenges.

Cutting the cabling to simplify the emulation process.

Companies need to collaborate with partners, vendors, and the rest of the supply chain if they are to achieve critical mass, Aart de Geus tells Synopsys user meeting.

Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey

This page brings together all of our coverage from Design Automation and Test in Europe 2012 in Dresden, Germany.

The International Symposium on Quality Electronic Design (ISQED) enters its 13th edition later this month, running March 19-21 at Techmart in Santa Clara. Although ISQED traditionally concentrated on tools and IP blocks, its agenda has broadened as the industry has migrated to SoCs and full electronic systems where process and manufacturing interactions have come to […]

A reference simulator for the latest version of SystemC is now available for public review and comment, writes Accellera's Dennis Brophy.