EDA needs to work on the back end, says Qualcomm
It’s the back-end that needs work as system-level considerations begin to dominate design, Qualcomm’s vice president of engineering said at DAC.
Author Archives: Chris Edwards
Remember the design gap? It’s back
Fifteen years on from the design gap that triggered the IP revolution, implementation costs have created a new one.
EDA learns to love AI
Machine learning is gradually moving into implementation and verification tools for EDA.
IoT devices need surprises, Amazon claims
IoT device makers should play more with their software and make use of techniques used in website design to increase overall usability, Amazon’s head of IoT analytics has claimed.
Cadence puts tools in the cloud
Cadence Design Systems has made a collection of its tools suitable for cloud computing, providing them for both Cadence- and customer-managed environments.
Node-variant FinFET tweaks try to improve cost, performance
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Imec stacks transistors for denser 3nm option
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
GlobalFoundries plays with metal gear in search for solid gains
At VLSI Symposia 2018, GlobalFoundries researchers proposed looking at the metal-gate ‘gear’ ratio as a way of improving the routability of standard cells.
AI is all about low-energy hardware says Dally
For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.
Samsung couples EUV with DTCO for 7nm shrink
Samsung Electronics expects to increase savings on die area in the shift from its 10nm to 7nm node by applying both EUV for critical layers and several layout-focused process changes.