November 12, 2013
Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
November 5, 2013
Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
November 5, 2013
Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
October 30, 2013
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
October 29, 2013
HP is throwing open its doors to other companies to bring in the necessary hardware and low-level software to build a new generation of servers, each specialized to a workload.
October 29, 2013
ARM has launched at TechCon its own crop of online forums intended to let engineers collaborate and share ideas and has asked for IoT ideas.
October 22, 2013
Memoir Systems has developed a set of memory controller IP cores that exploit common access patterns used by processors in network switches to improve performance and power consumption
October 16, 2013
Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.
October 11, 2013
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
October 10, 2013
Cadence Design Systems has launched IP cores for high-end mobile audio as well as gigasample ADCs for 28nm to support 60GHz wireless.