EDA

ARM has launched at TechCon its own crop of online forums intended to let engineers collaborate and share ideas and has asked for IoT ideas.

Memoir Systems has developed a set of memory controller IP cores that exploit common access patterns used by processors in network switches to improve performance and power consumption

Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.

Cadence Design Systems has launched IP cores for high-end mobile audio as well as gigasample ADCs for 28nm to support 60GHz wireless.

There's still time - just - to reserve your place at EDAC's Back To the Future dinner and auction to raise funds to mark EDA's contribution to our business at the Computer History Museum.

Cadence Design Systems has developed a version of its Spectre FastSpice tool that splits simulation across many computers without manually cutting the design into segments.

Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.

Design services company eSilicon has made freely available a tool it developed to streamline ordering for multi-project wafer (MPW) ‘shuttle’ services.

Research group CEA-Leti expects to have design kits ready for a 10nm FD-SOI process in June 2014