EDA

RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic blocks.

Dennard’s Scaling ended years ago and Moore’s Law is slowing down. What will the future hold for the semiconductor industry?

Last week's announcement by Avago that it would buy Broadcom looks to be only partly about bulk. The merger could help drive SIP and 3DIC integration.

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.

Design and manufacturing services company draws on big data to offer ASIC block optimisations

Startup Tortuga Logic has developed a toolkit for checking the security aspects of SoC hardware designs.

Sonics is moving into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs.