May 7, 2020
This case study shows how rising CMP simulation quality can be leveraged to detect the position and type of planarity hotspots before manufacture and verify the planarity of a layout.
July 23, 2014
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
July 15, 2014
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
January 13, 2014
If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
December 3, 2012
CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
June 1, 2012
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
May 22, 2012
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.