block-level

January 25, 2019

A better way to manage error reporting at the chip and block levels

In a continuous-build design flow, at which level should your error markers be addressed?
Article  |  Topics: EDA - IC Implementation  |  Tags: , , , , ,   |  Organizations:
October 16, 2018
Reliability verification feature - featured image

Reliability verification: It’s all about the baseline

How you can use the dedicated rule decks now being provided by foundries as the foundation for a reliability verification flow.

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