How you can decide what level of DRC you need when you need it

By Srinivas Velivala |  No Comments  |  Posted: May 31, 2021
Topics/Categories: EDA - DFM, - EDA Topics, EDA - IC Implementation, Verification  |  Tags: , , , , , , , , ,  | Organizations:

Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

Clearing complex and late-stage design rule checking (DRC) errors during digital integrated circuit (IC) implementation has always been time-consuming and resource-intensive. This is in part because of the way tools have evolved to support different stages in the design flow. Innovative functionality now allows P&R engineers to choose the level of DRC they need when they need it.

DRC using a full-featured tool and a foundry-qualified rule deck is required for designs to reach tapeout. It shows that the work satisfies the foundry’s process requirements for manufacturing. However, this level of checking is not really needed during early implementation stages where P&R engineers just need to clear obvious and (relatively) simple DRC issues like spacing or width. For that reason, P&R tools provide a built-in modified DRC deck that is designed to address the most common layout errors.

However, because this built-in DRC is neither foundry-qualified nor comprehensive, the P&R engineers will eventually reach the point where they need to perform a batch signoff DRC run on the layout to find and manually fix complex and late-stage errors. That means merging the P&R database with the IP to generate a merged GDSII/OASIS database, running batch signoff DRC, debugging the layout, making fixes in a local window, and then repeating the entire process to verify the fixes worked.

Of course, some of the fixes will not work, others may not be optimal. So the team will end up iterating this process multiple times. Since a batch DRC run typically takes anything from a few hours to overnight, and debugging time depends on how many and what kinds of errors the engineers see, this iterative verification flow can quickly become a costly schedule-killer.

And the thing is, it is also often overkill.

The P&R engineers don’t really need a full batch DRC run, but they do need signoff-quality DRC. If only there were a way to access signoff-quality DRC directly from the P&R tool…

Signoff DRC in P&R

The Calibre RealTime Digital interface from Siemens EDA, a part of Siemens Digital Industries Software, allows P&R engineers to access Calibre signoff DRC on-demand from within the P&R environment. The interface provides direct calls to Calibre analysis engines running foundry-qualified signoff Calibre rule decks (Figure 1), meaning engineers can perform any and all checks that can be run with the Calibre nmDRC platform, including pattern matching, equation- based DRC, preferred metal direction rules, multi-patterning, and even recommended rules for design for manufacturing (DFM) optimization.

The Calibre engines perform fast, incremental checking near shapes being edited and, through the Calibre RealTime Digital interface, provide nearly instantaneous feedback on DRC violations. This immediate feedback in the P&R domain enables engineers to implement and check fixes with signoff quality, but without the need for full DRC iterations. Because these checks typically take only seconds to minutes, engineers can perform multiple iterations in far less time than one batch DRC run.

Figure 1.The Calibre RealTime Digital DRC flow enables multiple, fast DRC fix-verify iterations during P&Rn (Siemens).

Figure 1. Figure 1. The Calibre RealTime Digital DRC flow enables multiple, fast DRC fix-verify iterations during P&R (Siemens).

One immediately obvious advantage of this speed-up is that engineers can now quickly try multiple fix options to determine which one best fits the design goals for power, performance and area (PPA). Then, because they have access to a full range of checks, they can also implement various layout options to optimize DFM scores.

Let’s take a look at just some of the ways design companies are using on-demand signoff-quality DRC in their P&R flows.

Last-mile DRC for full-chip designs
Interface errors between top-level and hierarchical blocks can be particularly challenging to fix and verify. The Calibre RealTime Digital interface can intelligently merge only the required shapes from top-level and hierarchical blocks, launch a DRC run, and highlight both the DRC error marker and the IP shapes around the error marker in the P&R tool. Designers can then validate the interface DRC fixes without leaving the P&R environment.

The increased pin density at each new node makes it difficult for the P&R routing engine to access the pins during routing without causing DRC errors, such as diagonal via spacing violations created when routing to AOI and OAI cells. To fix these , engineers must move the vias while ensuring no new violations are generated. The Calibre RealTime Digital in-design DRC provides immediate signoff-quality feedback on placement fixes for fast validation in the P&R environment.

IP integration

IP integration can be challenging, particularly for actions like determining halo requirements around integrated IP and highlighting placement restrictions at the top level (e.g., back-to-back memories, digital/analog keepouts, IO pad halos). Using Calibre RealTime Digital on-demand signoff DRC, designers start to see DRC violations when the IP is moved within just a few microns of the standard row cells. With a runtime measured in seconds, the feature lets engineers determine the optimum distance for IP halos while also minimizing area.

Likewise, abutment errors in memory placements can be quickly spotted and adjusted. Moreover, any false or waivable DRC errors can be removed from subsequent runs.

Via selection

Foundries typically provide four types of via: single-cut, single-cut with extended enclosure, via-bar, and multi-cut. Calibre RealTime Digital simplifies the task of swapping one type for another. Engineers can swap in new types, use the in-design DRC in a local window to catch any DRC errors created by the swap, apply fixes, and then quickly validate again to ensure the layout is DRC-clean. They can also recheck DFM scores after completing multiple via swaps, something they typically want to do when they are near or have achieved their target DFM score.

Multi-patterning

Fixing multi-patterning errors typically requires multiple rounds of what-if analysis on the layout by making a manual fix and then waiting for DRC feedback. With immediate signoff DRC feedback on each manual edit, P&R engineers can determine and implement the optimum fixes quickly and confidently.

ECO errors

Sometimes, when a design is close to tapeout, either a functional or timing error requires an engineering change order (ECO) layout adjustment that can result in a signal short. P&R engineers typically prefer to manually fix the short to avoid any alteration to the surrounding nets. With the Calibre RealTime Digital interface, they can manually fix the short in the P&R environment, and use the immediate DRC feedback to verify that the edits have not caused any DRC errors.

Occasionally, after a design has been sent to the foundry for manufacturing, unexpected ECOs will be needed. When this happens, the foundry requires the design company to run special re-tapeout (RTO) checks before returning the design with the ECO changes. These checks must be run because the mask for the layer is already prepared, which adds more constraints to the location of the geometries. With Calibre RealTime Digital, engineers can interactively verify their fixes for the RTO DRC issues, and quickly send the design back for fabrication.

Early rule exploration

One of the challenges in moving to a new node is quickly understanding how to apply new and expanded rules. Historically, this meant settling in for an often tedious read of descriptions of complex design rules and their checks. With on-demand signoff DRC in the P&R environment, engineers can simply perform a what-if analysis within the P&R tool and quickly both see and understand the parameters and application of a rule. For example, layout restrictions for standard cell symmetry or cut metal can be much easier to understand if you can watch the actual application of the rule to a given layout. In fast-moving markets, even the few days’ advantage such features can offer will help a company achieve greater success.

Conclusion

On-demand signoff DRC helps P&R engineers move through design implementation much more quickly. It gives them full confidence that any fixes and optimizations they apply are ‘correct by construction’.

To achieve maximum yield while ensuring optimized performance, power, and area, and to do it within today’s demanding schedules, requires design companies to take advantage of any innovative technology that allows them to produce better results in less time. The ability to switch between the built-in P&R DRC and the signoff-quality DRC allows design teams to have what they need when they need it.

Further reading

Inphi Case Study: Improving Digital Design Productivity

MaxLinear and Calibre RealTime Digital: Signoff DRC in P&R

Fix DFM hotspots in P&R with Calibre sign-off confidence

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