Synopsys

June 13, 2019

The road to ES Design West: AI

AI, its system design implications and its impact on EDA tools themselves will be a key theme for ES Design West next month.
June 12, 2019

Energy-efficient implementation of machine-learning algorithms for IoT

White paper goes from general principles through to worked examples of efficient machine-learning algorithm implmentations on dedicated processor IP.
Article  |  Topics: Blog - IP, - Technical Articles  |  Tags: , , ,   |  Organizations:
June 4, 2019

DAC to colocate with Semicon West next year

SEMI and the Design Automation Conference (DAC) have agreed to schedule the the US event for EDA alongside Semicon West in 2020 and 2021.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , ,
June 3, 2019

Analyst: China’s foreign EDA thirst to grow despite trade tensions

Analyst Rich Valera points to China as a major source of EDA tool growth despite short-term tensions with the US government.
May 29, 2019

Synopsys introduces fast full-chip yield analysis and optimization tool

Synopsys has released PrimeYield, a tool for analysing and optimizing the yield of a design before it is made.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations:
February 6, 2019

Safety and test IP heads for automotive AI applications

Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
Article  |  Topics: Blog - IP  |  Tags: , , ,   |  Organizations:
January 21, 2019

Video series details the physical verification process

Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , ,   |  Organizations:
December 14, 2018

Synopsys announces DDR5 and LPDDR5 interface IP

Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: , , ,
November 30, 2018

Design Compiler updated for 5nm and beyond

Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Article  |  Topics: Blog - EDA  |  Tags: ,   |  Organizations:
October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
Article  |  Topics: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,   |  Organizations: , ,

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