EDA

Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.

Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more

Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.

The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.

Cadence Design Systems has launched IP cores for high-end mobile audio as well as gigasample ADCs for 28nm to support 60GHz wireless.

There's still time - just - to reserve your place at EDAC's Back To the Future dinner and auction to raise funds to mark EDA's contribution to our business at the Computer History Museum.

Cadence Design Systems has developed a version of its Spectre FastSpice tool that splits simulation across many computers without manually cutting the design into segments.

The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.

Real-value modelling and flows using the Open Access database will be among the focus topics of Cadence's Mixed-Signal Technology Summit on 10 October.

For the new web TV program Unhinged, Brian Fuller talked to venture capitalist Jim Hogan about the future of mixed-signal and the past of EDA.