Cadence Design Systems is hosting a Mixed-Signal Technology Summit at its headquarters in San Jose this Thursday (10 October) that will focus on the latest in design techniques such as wreal or real-number modelling.
As described in our Guide, wreal modelling can be used to simulate the functions of analog blocks within a larger predominantly digital simulation. The simulation allows wires within a simulation in SystemVerilog or similar language carry a real-number value and so provide analog-like characteristics for modules designed to interpret those values. Several updates are on the way to the language that will ease modelling with wreals, including the ability to deal with multiple drivers on a net.
During the Summit, Bhupi Manola of Cirrus Logic will talk about the company’s use of wreal modelling and Cadence’s Michael Hufford will describe the technique’s use in verifying serdes bit-error rates.
Focusing on other parts of the flow, STMicroelectronics’ Livio Fratantonio will cover the company’s ‘smart power’ flow and the Open Access database’s role in design will form the heart of presentations from Microsemi and Rambus.
The Cadence Summit will cover the latest updates to the company’s tools, such as the electrically aware flow and wreal simulation support, and kicks off with a keynote looking at emerging mixed-signal applications by Professor Terri Fiez of Oregon State University.