Jasper preps User Group and Architectural events

By Paul Dempsey |  No Comments  |  Posted: October 9, 2013
Topics/Categories: Blog Topics, Conferences  |  Tags: , , , ,  | Organizations:

EDA vendor Jasper Design Automation will hold its 2013 User Group Meeting  in Cupertino, California on October 22-23 followed by the company’s Architectural Formal Verification Forum on October 24. Both events roll out at the Cypress Hotel.

A new element is a series of Birds of a Feather breakfast meet-ups aimed at giving users still more input into the specific design challenges discussed at the User Group. The high-level topics for these more informal sessions are:

  • Proof Grid
  • Property synthesis
  • Clock & reset set up and verification
  • Low power verification
  • AMBA Proofkit certification
  • Protocol verification
  • Security path verification

BoF sessions run from 8am-9.30am on both days of the User Group, with the main presentation sessions scheduled from 9.30am-5pm. The presentation sessions will cover both existing design challenges and incoming tools or technologies. Specific topics under review cover a broad range and the foremost are:

  • Designer-based verification
  • Sequential equivalence checking
  • Architecture validation
  • Low power verification
  • Coverage
  • Security path verification
  • SoC integration
  • Property synthesis
  • Post-silicon debug
  • Verification IP
  • Formal property verification
  • Jasper technology roadmap
  • Glimpse of future technology

Jasper Architectural Formal Verification Forum

Jasper’s Architectural Formal Verification Forum concentrates on modeling as well as advanced verification techniques. The format for the event is designed around both presentations and discussions. The company is looking to generate user feedback on both its existing technologies and its roadmap

Some of the main areas that will be addressed are:

  • Leverage of a unified model for (a) architecture verification and (b) VIP for downstream RTL verification
  • Architectural modeling and deadlock verification of interconnects
  • Deadlock detection
  • Architectural coverage vs. design coverage
  • Advanced formal techniques for computationally efficient architectural modeling and verification
  • JasperGold Architectural Modeling App for power-architecture modeling and verification

The forum runs from 9am-6pm.

To register for the Jasper User Group, click here.

To register for the Jasper Architectural Formal Verification Forum, click here.

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