Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
EDA
Symphony raises crescendo for AMS simulation
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Cadence adds deep-learning support to audio DSP
Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
Mentor extends Tessent for debug and automotive pattern generation
As ITC 2018 begins, Mentor addresses stringent ISO 26262 requirements and looks to bridge the gap in how IJTAG-based debug is structured.
FPGA playing verification catch-up as bugs escape
The latest Mentor-commissioned Wilson Research Group study on ASIC and FPGA verification highlights technique adoption and maturity.
UltraSoC combines tools for cross-SoC debug and analysis
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
White paper outlines challenges of developing machine-learning hardware
A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.
Module strategies try to streamline IoT trials
Suppliers to the embedded industry see modules and readymade software as being key to getting IoT projects off the ground.
Cadence culls zeroes for faster neural throughput
Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.