Taking an IoT edge design from proof-of-concept to prototype
A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
EDA
Safety and test IP heads for automotive AI applications
Automotive AI specialist FABU has licensed a portfolio of IP from Synopsys to help assemble ISO 26262-compliant SoCs
Fast process access gets Moortec onto 7nm
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
Creating a $4B market for silicon photonics
It's been a long time coming, but silicon photonics is now entering commercial design for networking and grabbing attention in autonomous driving and sensors.
Video series details the physical verification process
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Closing code coverage with a hardware-aware HLS-to-RTL flow
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Why Mentor backs the PSS-DSL input format for the Portable Stimulus Specification
With PSS moving toward greater adoption, the Siemens vendor seems PSS-DSL as a winner in terms of conciseness and ease-of-adoption.
Synopsys announces DDR5 and LPDDR5 interface IP
Synopsys is targeting artificial intelligence (AI) and data centre SoCs as key application areas for the interface IP.
Design Compiler updated for 5nm and beyond
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Xpedition updated for schematic verification and DFT
Mentor's flagship PCB suite is aiming to offer another 'shift left' in verification as respins rise.