Archives

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.

CEVA has reworked its XC architecture to provide what the company claims is the kind of performance boost needed to handle phase-two 5G applications once Release 17 rolls out.

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Wind River has set up a site to distribute more experimental libraries based around its real-time operating systems and provide a hub for users to interact.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV's DVCon program.

Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor's Embedded World agenda.

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.