Archives

July 9, 2013

Xilinx tapes out for first of 20nm-generation FPGAs

Xilinx aims to be first of the FPGA makers to produce 20nm devices, expecting to move to production samples for some products by the end of the year.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , , , ,   |  Organizations:
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,
June 19, 2013

nVidia to license GPU technology as IP cores

Graphics chipmaker nVidia has said it plans to license as IP cores some of its technology in the hope of building up a customer base among other chipmakers and systems houses developing their own SoCs.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , ,   |  Organizations: ,
June 18, 2013

Microsemi focuses on security with Igloo2 FPGAs

Design security is a major target for Microsemi’s update to its Igloo series of flash memory-based FPGAs, which add an ARM-oriented memory subsystem.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:
June 18, 2013

Real Intent highlights hierarchical clock domain crossing with Meridian 5.0

SystemVerilog and Synopsys Verdi integration are among further enhancements as clock domain crossing competition intensifies.
Article  |  Topics: Blog - EDA, - RTL, Verification  |  Tags: , ,   |  Organizations: ,
June 17, 2013

Atmel bridges 8 and 32bit gap with ARM M0+ family

Atmel has launched its first family of microcontrollers based on ARM's Cortex M0+ with features to ease PCB design and provide programmable serial ports.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , ,   |  Organizations:
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
June 10, 2013

Altera outlines process roadmap for ‘Gen 10’ FPGAs

Altera has disclosed a number of the features that will make it into the top end of its upcoming 'Generation 10' family of FPGAs.
Article  |  Topics: Blog - EDA, PCB  |  Tags: , , , , ,   |  Organizations: , ,
June 5, 2013

Jasper, Duolog bring formal verification to IP specification and assembly, low-power design

Deal creates methodologies and tools to help deliver IP and SoC assemblies verified using formal methods. Low-power verification strategy also launched.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: ,   |  Organizations: ,
June 3, 2013

Embedded world ‘needs EDA’s models’

The EDA industry has a way to capture the embedded software market, analyst Gary Smith said ahead of DAC. But it’s not through tools – it’s through models.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , ,   |  Organizations: