Archives

The latest revision of the IEEE 1801 Unified Power Format standard for verifying low-power designs has been made available through the IEEE Get Program.

Xilinx and TSMC are forming a single engineering team to accelerate development of a family of finFET-based field programmable gate arrays (FPGAs).

Wire harness margins are tight yet quotes still need to be turned on a dime. Integrating that process into existing tools aims to help.

Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group

Vehicle-maker Volkswagen is putting its weight behind a set of microcontroller benchmarks that focus on energy consumption rather than performance.

Spec-TRACER addresses stringent design reporting demands in safety-critical markets, some of which are moving into the mainstream.

Cadence Design Systems has launched a timing-signoff tool that uses parallel processing and place-and-route algorithms to try to speed up time to tapeout.

Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.

Physical-IP startup SureCore has been awarded $380,000 to build a demo chip for a low-power SRAM design the company is aiming at finFET and FD-SOI processes.

Altera has bought fabless power-management specialist Enpirion in an expansion intended to support its core business of FPGAs.