On-chip interconnect startup uses network theory to sidestep deadlocks
NetSpeed Systems aims to cut SoC integration time using theories developed for much larger computer networks.
Archives
Mentor seeks component data in PCB design tie-up with Digi-Key
Digi-Key is to sell software developed by Mentor Graphics intended to widen access to PCB design and ease access to vital parts data.
Imagination in push for Java and open source
Imagination Technologies has set up an open-source effort that mirrors ARM's Linaro group and cut a deal with Oracle for Java optimization.
Pulsic opts for “layout early, layout often” strategy
Pulsic has developed an automated mixed-signal layout tool that uses multiple generated variants to let designers pick the best implementation.
Multicore fastSpice extends reach
Cadence has expanded the reach of its parallelized fastSpice engine and Spectre XPS tool to support general-purpose analog and mixed-signal designs.
Cadence signs with ARM for core optimizations
Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
Cadence ports IP and qualifies tools for 28nm FD-SOI
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Samsung agrees to make 28nm FD-SOI
STMicroelectronics has found an alternative production partner for the FD-SOI process that the European chipmaker is presenting as an easier option for SoC designers.
Mentor targets 10X cut in reliability test for power electronics
New MicReD power tester identifies failure causes without the need for post-test lab analysis
Synopsys speeds HAPS prototyping with ProtoCompiler
HAPS-specific enhancements to Synplify and Certify join next gen partitioning and planning in suite that claims 3X boost in time-to-prototype