Path to 5nm plotted at DAC panel
Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound
Archives
Verilog-AMS release adds to power-aware analog modeling
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.
Cliff Hou, TSMC VP R&D, on the route to 10nm – and beyond
Head of TSMC R&D talks about what it will take to develop and use 10nm, 7nm processes, and a possible shift to using packaging to extend Moore's law scaling
3D and EDA need to make up for Moore’s Law, says Qualcomm
Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase.
Remember 20nm? Qualcomm does
Qualcomm will present at VLSI Technology Symposium 2014 a version of TSMC's 20nm technology that uses design and process tweaks to reduce the number of double-patterned layers.
Chipmaking’s future: all of the nodes all of the time
The stall in Moore's Law caused by the rapid rise in cost of the advanced processes will shift more innovation to mature nodes Monday keynoters at DAC said.
Samsung certifies Synopsys tools, IP at 14nm
Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
Synopsys uses virtual prototyping kits to kick start IP integration
Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
Emulation ‘heart of ESL’
The emulator has become the cornerstone of embedded system level (ESL) design on SoC projects, analyst Gary Smith claimed in a speech ahead of DAC 51.
Synopsys adds vector DSP operations to ARC EM processor IP
Synopsys has developed a digital signal processing (DSP) instruction set extension to its EM family and two cores that employ it.