DAC 2017 preview: Mentor
Mentor, a Siemens business, has posted its main landing page for its activities at the 2017 Design Automation Conference (DAC 2017) taking place in Austin, Texas later this month (June 18-22).
As last year, the company is spreading its activities across three booths, the main Mentor stand (947) with separate and additional presences for its Tanner EDA division (1129) and the Verification Academy (429). All can be found in the main hall of the Austin Convention Center.
Following the company’s recent acquisition by Siemens, two Mentor speakers are likely to draw large audiences and some close listeners.
Wally Rhines, Chairman and CEO, will feature in a one-to-one interview with editor Ed Sperling at 11:30AM on Wednesday June 21 in the DAC Pavilion (located on the exhibit floor).
Meanwhile, Chuck Grindstaff, Executive Chairman of Siemens PLM Software, is to be one of this year’s DAC 2017 keynote speakers. His topic is ‘The Age of Digital Transformation’, and he will discuss the move toward systems of systems as well as the need for greater design automation throughout the industrial design process. The keynote begins at 9:00AM on Tuesday June 20 in Ballroom A.
Other Mentor highlights at DAC 2017 include the following.
DAC 2017 technical conference
Mentor staff are participating in one high profile tutorial and will also individually or jointly present eight papers as part of the main conference at DAC 2017 (all events take place in the Austin Convention Center and times and dates were correct at time of posting, but please check links for them before attending in case of schedule changes):
Tutorial
Mentor’s Tom Fitzpatrick has organized and will join colleagues from Breker Verification Systems, Cadence Design Systems, Intel, Synopsys and Vayavya Labs at what for many will be a must-attend tutorial providing An Introduction to the Accellera Portable Stimulus Standard. It takes place from 1:30-3:00PM on Monday June 19 in Room 18CD.
Conference papers
‘Comprehensive Power Rail Constraint Verification for Large Analog Designs at an Early Stage’ – with Renesas System Design (Session 5, 1:30-3:00PM, Monday June 19, Ballroom F).
‘Physics-Based Electromigration Assessment for Analysis of EM Degradation in 3D IC Test Structures’ – with the University of Toronto and CEA-Leti Minatec (Session 5, 1:30-3:00PM, Monday June 19, Ballroom F).
‘Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP Formulation’ – with the Democritus University of Thrace (Session 31, 3:30-5:30PM, Tuesday June 20, Room 18AB).
‘Leveraging Security to Increase the Value of Your Chips in the Supply Chain and the Field’ (Session 32, 3:30-5:00PM, Tuesday June 20, Ballroom E)
‘Novel Approach to Hardware Software Co-Verification on Emulation’ – with Cavium (Session 49, 1:30-3:00PM, Wednesday June 21, Ballroom F).
‘Thermal Exploration and Sign-Off Analysis for Advanced 3D Integration’ – with CEA Leti (Session 49, 1:30-3:00PM, Wednesday June 21, Ballroom F).
‘Generic UVM-Based Verification Architecture for Flash Memory Controllers’ – (Session 50, 1:30-3:00PM, Wednesday June 21, Ballroom G).
‘A Novel ECO Solution for Sequential Clock Gating Based Low Power Design Flow’ – with Samsung Electronics (Session 57, Wednesday June 21, 3:30-5:00PM, Ballroom E).
On the Mentor stand
Mentor’s landing page also provides details and registration for a number of company-organized events that will be taking place on its stand and elsewhere.
These include include panels on creating custom SoCs for the Internet of Things, how the ISO 26262 automotive functional safety standard is having an impact on fabless companies, and the ongoing proliferation in models for the use of emulation. You will also find details of further technical sessions, and Mentor’s Calibre-led luncheon session on Monday June 19.
Mentor has also blogged about its DAC 2017 activities.
