DAC 2017 preview: Synopsys

By Luke Collins |  No Comments  |  Posted: June 1, 2017
Topics/Categories: Conferences  |  Tags:  | Organizations: , , , , , ,

Synopsys has posted its main landing page for its activities at the 2017 Design Automation Conference (DAC 2017) taking place in Austin, Texas later this month (June 18-22).

Aart de Geus, Chairman and CEO, will feature in a one-to-one interview with editor Ed Sperling at 11:30AM on Tuesday June 20 in the DAC Pavilion (located on the exhibit floor). He’ll talk about the rise of “smart” everything — the third generation of electronics, including insights about the drivers, the important trends, and the future possibilities for the silicon-to-software ecosystem.

This silicon-to-software focus, which has long been a part of Synopsys’ strategy, will also be reflected in Synopsys’ Silicon to Software Theater on the show floor, where speakers including industry experts and Synopsys R&D representatives are expected to talk about industry trends and technology challenges facing the FinFET, IoT, automotive, and mobile computing market segments.

Synopsys will hold a series of special events, with partners including ARM, Intel Foundry, GLOBALFOUNDRIES, Samsung, and TSMC. It will also be involved in events with other partners and standards bodies, details of which can be found here.

Synopsys staff will also take part in a high-profile tutorial and will also individually or jointly present a number of other papers as part of the main conference at DAC 2017 (all events take place in the Austin Convention Center and times and dates were correct at time of posting, but please check links for them before attending in case of schedule changes).


Synopsys will participate, alongside colleagues from Breker Verification Systems, Cadence Design Systems, Intel, Mentor Graphics, and Vayavya Labs, at what for many will be a must-attend tutorial providing An Introduction to the Accellera Portable Stimulus Standard. It takes place from 1:30-3:00PM on Monday June 19 in Room 18CD.

Conference presentations

Tutorial 4: machine learning and systems for building the next generation EDA tools

Monday June 19, 10:30AM – 12:00PM Room 18CD

This tutorial covers the basics of machine learning, systems and infrastructure considerations for performing machine learning at scale, specialized hardware architectures for neural networks, and approaches for using machine learning for building the next generation of EDA tools.

Tutorial 6: Logic synthesis is everywhere

Monday 19 June, 1:30PM – 3:00PM, Room 18AB

The tutorial covers three parts: (i) the use of Boolean satisfiability techniques to scale logic synthesis algorithms, (ii) new data structures and algorithms for delay optimization, and (iii) the application of logic synthesis in the design of quantum computers.

SESSION 36.4: iClaire: A Fast and General Layout Pattern Classification Algorithm

Wednesday 21 June, 10:30AM to 12:00PM, Room 18CD

Lithography layout decomposition and hotspot pattern detection are critical and indispensable processes for today’s high-performance chip design and manufacturing. The session starts with a powerful fixed parametric tractable algorithm targeting at the layout decomposition problem. The session then presents a specialized deep neural network for hotspot pattern detection. The last part of the session consists of two improved solutions for layout pattern classification problem presented in 2016 ICCAD contest.

SESSION 50: IP Strategies for Reducing Time-to-Market of Complex SoCs

Wednesday 21 June, 1:30PM to 3:00PM, Ballroom G

Ad-hoc verification strategies are no longer sufficient to guarantee operational silicon and the current lack of a solid methodology to handle the evolution of individual IPs in the context of the complete design only exacerbates the problem. In this session six speakers each present their view on how to solve different aspects of the IP handling and verification challenge.

Chair: Paul Stravers, Synopsys, Eindhoven, The Netherlands

Session 57.5: Power Estimation Acceleration Based on Distributed Emulation

Wednesday 21 June, 3:30PM to 5:00PM, Ballroom E

In this era of exploding cell phones, it is more critical than ever to consider power issues from the very beginning of the design and validation process. This session will explore a variety of approaches for proactively handling power-related challenges at the front end.

Poster session 124.4: SoC Netlist Clock Domain Crossing Verification with Abstract Model Approach

Wednesday 21 June, 5:00PM to 6:00PM, Exhibit Floor

Poster session 124.6: Formal Connectivity Checking Coverage Metrics

Wednesday 21 June, 5:00PM to 6:00PM, Exhibit Floor

Speaker: Anders Nordstrom, Synopsys, Ottawa, Ontario, Canada

Session 66.2: A New Paradigm for Synthesis of Linear Decompressors
Thursday 22 June, 1:30PM  to 3:00PM, Room 15

This sessions covers advances in test technologies to address the emerging needs of memristor-based storage systems and asynchronous circuits. The continued increase of test data volume requires new solutions for test compression, while software solutions offer new alternatives for soft-error tolerance.

Session 75: #Alt_Computing: Make Use of Emerging Technologies
Thursday 22 June, 3:30PM to 5:30PM, Room 18CD

This session showcases 6 papers covering quantum computing and other emerging technologies.

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