DAC to train on machine learning

By Chris Edwards |  No Comments  |  Posted: May 19, 2017
Topics/Categories: Blog - EDA, Embedded  |  Tags: , , , ,  | Organizations:

DAC’s traditional Thursday training day is expanding into the field of machine learning this year in Austin.

Following a teaser lunch session on Python in machine learning, Doulos will follow up on Thursday with a half-day course on the programming language.

On Wednesday, the one-hour taster session, which includes lunch is provided by Doulos and sponsored by Synopsys. On Thursday attendees may choose sessions from three parallel tracks with the option to select both the morning and afternoon sessions from the same track, or mix-and-match sessions from two different tracks or attend a single half-day session. Training sessions on SystemVerilog, UVM, and Python are taught by Doulos and C++ by Trull Consulting.

The 54th DAC will be held at the Austin Convention Center in Austin, Texas June 18- 22, 2017.

Registration for the Wednesday Lunch ‘N’ Learn.

Thursday is Training Day Tracks:
Track 1: System Verilog & UVM Coding
Part 1: How to Build Class-Based Verification Environments in SystemVerilog
Part 2: Learn UVM using the Easier UVM Coding Guidelines and Code Generator
Track 2: System Verilog Verification and Python Language
Part 1: Formal Verification using SystemVerilog Assertions
Part 2: The Python Language: Become a Pythoneer!
Track 3: Raising your C++ Game (two parts)

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors